Calibre 3DThermal
Chiplet and Die Junction-Temperature Analysis at Sign-Off Fidelity
Junction-temperature analysis at the chiplet and die level — the layer where advanced-package thermal problems actually originate.
What It Is
Calibre 3DThermal analyses heat flow inside the die and across chiplet-to-substrate interfaces using the same physical basis Calibre already uses for sign-off. It is where thermal joins physical verification.
Core Capabilities
Chiplet-level junction temperature
- Resolve per-tile and per-transistor junction temperature in advanced-node designs.
- Analyse hot-spot interaction across stacked die.
- Support 2.5D and 3D-IC architectures.
Physical-verification-grade solver
- Uses the Calibre nmDRC / nmLVS engine your sign-off flow already trusts.
- Reads GDS and OASIS layout directly.
- Fits naturally into the physical-design flow.
Best For
- Advanced-node SoCs
- Chiplet and 2.5D / 3D-IC designs
- AI accelerators
- High-bandwidth-memory stacks
- Automotive SoCs qualifying under AEC-Q100
Six-stage workflow position
Why engineering teams choose Calibre 3DThermal.
Representative engineering situations these tools are asked to resolve.
- 01
A chiplet-based accelerator throttles under sustained inference load even though the package-level model shows 12 °C of margin. Package thermal averages power across the die; Calibre 3DThermal resolves per-tile gradients and finds a 200 µm dense-logic region running 18 °C above the die average — invisible to any model whose smallest thermal element is the whole die.
- 02
A stacked HBM design must ship a JEP30 PartModel to an OEM before the OEM will start its system thermal work. Calibre 3DThermal produces the die-level power and temperature basis the compact model needs, so the deliverable rests on layout-accurate analysis rather than a uniform-flux approximation.
- 03
A 2.5D floorplan passes average-power review at 350 W but loses setup margin on one compute tile in silicon. Calibre 3DThermal reads the GDS directly and exposes a 15 °C local gradient at that tile pre-tapeout, when a floorplan move still costs days instead of a respin.
- JEDEC JEP30 PartModel (May 2024)
- OCP chiplet CDXML thermal
- AEC-Q100 junction-temperature basis
- Physical-design engineer
- Package engineer
- Thermal engineer
How this reaches your team.
Delivered by Electro Source with flow integration into your existing Calibre sign-off environment, and workflow bridging to Innovator3D IC for package-level exchange.
Discuss Your Chiplet Thermal Question
Tell us the architecture — chiplet count, stack, memory — and the junction-temperature question you need answered.