How do I manage the thermal density of a SiC or GaN design that switches faster and runs hotter than the silicon it replaced?
Wide-bandgap devices let designers shrink power stages and raise switching frequency, but the same devices concentrate more heat into a smaller die area and are frequently pushed to higher junction temperature limits than the silicon designs they replace — which means thermal margins that worked before no longer apply.
Faster switching also changes the thermal-mechanical stress profile at the die-attach and package interconnects, and TIM and cold-plate designs sized for a lower-density silicon module may not hold up under a SiC or GaN module's transient thermal excursions.
- SiC and GaN devices operate at higher power density and often higher rated junction temperature than the silicon devices they replace, invalidating thermal margins from prior designs
- Faster switching frequencies change the transient thermal-mechanical stress profile at die-attach and interconnects, which steady-state thermal models don't capture
- TIM and cold-plate designs proven on lower-density modules may not provide adequate heat removal at the higher local flux of a wide-bandgap device
- Package parasitics and thermal path in wide-bandgap modules are often new designs without an established measurement baseline
- Reliability data (power-cycling life) for wide-bandgap packages is less mature than for established silicon devices, so qualification often has to be built from scratch rather than referenced from existing data
- Simulate high-power-density thermal behavior including two-phase cold-plate and cooling loop options in STAR-CCM+
- Model board, enclosure and system-level cooling for the power module in Flotherm
- Characterize the wide-bandgap module's thermal transient response and structure function with Simcenter Micred T3Ster
- Qualify power-cycling reliability at the device's actual switching duty cycle with Simcenter Micred Power Tester
- Characterize TIM performance at the module interface with Simcenter Micred DynTIM
- Use measured thermal resistance and TIM data as the boundary conditions for the cooling and cold-plate simulation, rather than reusing assumptions from a prior silicon design
- Feed power-cycling degradation data back into the thermal simulation to set realistic end-of-life margin for the higher-density design
High-power-density and two-phase cooling simulation
Board, enclosure and system-level cooling for the power module
Thermal transient characterization of the wide-bandgap module
Power-cycling reliability qualification at actual switching duty
TIM characterization at the module interface
- AQG 324 power cycling qualification
- JEDEC JESD51 package characterization
Re-baseline your thermal margins for wide-bandgap power density.
Tell us the device (SiC/GaN), power density and switching frequency, and we'll help you set up simulation and measurement correlation for it.